#ifndef STM32F1_SCB_H_
#define STM32F1_SCB_H_

#include <stdint.h>
#include "iodef.h"

typedef struct
{
        __I  uint32_t CPUID;   /* Offset: 0x00  CPU ID Base Register                                  */
        __IO uint32_t ICSR;    /* Offset: 0x04  Interrupt Control State Register                      */
        __IO uint32_t VTOR;    /* Offset: 0x08  Vector Table Offset Register                          */
        __IO uint32_t AIRCR;   /* Offset: 0x0C  Application Interrupt / Reset Control Register        */
        __IO uint32_t SCR;     /* Offset: 0x10  System Control Register                               */
        __IO uint32_t CCR;     /* Offset: 0x14  Configuration Control Register                        */
        __IO uint8_t  SHP[12]; /* Offset: 0x18  System Handlers Priority Registers (4-7, 8-11, 12-15) */
        __IO uint32_t SHCSR;   /* Offset: 0x24  System Handler Control and State Register             */
        __IO uint32_t CFSR;    /* Offset: 0x28  Configurable Fault Status Register                    */
        __IO uint32_t HFSR;    /* Offset: 0x2C  Hard Fault Status Register                            */
        __IO uint32_t DFSR;    /* Offset: 0x30  Debug Fault Status Register                           */
        __IO uint32_t MMFAR;   /* Offset: 0x34  Mem Manage Address Register                           */
        __IO uint32_t BFAR;    /* Offset: 0x38  Bus Fault Address Register                            */
        __IO uint32_t AFSR;    /* Offset: 0x3C  Auxiliary Fault Status Register                       */
        __I  uint32_t PFR[2];  /* Offset: 0x40  Processor Feature Register                            */
        __I  uint32_t DFR;     /* Offset: 0x48  Debug Feature Register                                */
        __I  uint32_t ADR;     /* Offset: 0x4C  Auxiliary Feature Register                            */
        __I  uint32_t MMFR[4]; /* Offset: 0x50  Memory Model Feature Register                         */
        __I  uint32_t ISAR[5]; /* Offset: 0x60  ISA Feature Register                                  */
}scb_reg_t;

#define SCB_ICSR_VECTACTIVE_MASK        _VALUE(0, 0x1FF)
#define SCB_ICSR_RETTOBASE              _BIT(11)
#define SCB_ICSR_VECTPENDING_MASK       _VALUE(12, 0x1FF)
#define SCB_ICSR_ISRPENDING             _BIT(22)
#define SCB_ICSR_ISRPREEMPT             _BIT(23)
#define SCB_ICSR_PENDSTCLR              _BIT(25)
#define SCB_ICSR_PENDSTSET              _BIT(26)
#define SCB_ICSR_PENDSVCLR              _BIT(27)
#define SCB_ICSR_PENDSVSET              _BIT(28)
#define SCB_ICSR_NMIPENDSET             _BIT(31)

#define SCB_AIRCR_SYSRESETREQ           _BIT(2)
#define SCB_AIRCR_PRIGROUP_MASK         _VALUE(8, 0x7)
#define SCB_AIRCR_PRIGROUP(n)           _VALUE(8, ((n) & 0x07))
#define SCB_AIRCR_VECTKEY_MASK          _VALUE(16, 0xFFFF)
#define SCB_AIRCR_VECTKEY               _VALUE(16, 0x05FA)

#define SCB     ((scb_reg_t *)SCB_BASE)

#endif /* STM32F1_SCB_H_ */

